Layouts for analog circuitry usually satisfy certain geometrical and topological layout constraints that enable the circuitry to function correctly and to comply with design specifications. Such geometrical and topological layout constraints include for example symmetries between components, absolute placement positions, relative placement positions, relative orientations of one type of components with regard to another type of components and similar constraints. During migration of analog layouts for analog integrated circuits from a manufacturing technology to layouts manufactured in another, e.g. more contemporary technology, such as from a 55 nm to a 40 nm CMOS manufacturing technology, the existing symmetries, alignments and regularities of the components'placement and wiring should be translated to the new design as precisely as possible.
Due to the high number count of components in modern circuitry analog layout constraints should be detectable automatically in order to reduce the amount of time and design expertise needed for migration. Existing solutions for automatic layout migration employ procedures that tend to over-constrain the compaction problem, which may result in long runtimes or even the failure to find a solution at all. For example, the methods for analog layout migration in documents U.S. Pat. Nos. 7,665,054 B1, 7,418,683 B1 and 7,086,020 B1 rely on the user's expertise and netlists of source objects.